# Injected fault: BRESP changes while stalled

Result: VIOLATIONS_FOUND

Input: synthetic hand-authored protocol edge samples; not captured RTL or hardware

Checker: Header7F selected AXI trace monitor v0.1.0 (MIT)

## Observed samples

9 consecutive edge samples; AW accepted 1, W accepted 1, B accepted 1.

## Violations

- Cycle 6: H7F_AXI_BRESP_HOLD — BRESP changed from 0 to 2 while a response was awaiting acceptance.

## Selected rules and sources

- H7F_AXI_BVALID_HOLD: Hold BVALID until the response is accepted. AMD PG101 v2.0, check 35: AXI_ERRS_BVALID_STABLE. https://docs.amd.com/r/en-US/pg101-axi-protocol-checker/AXI-Protocol-Checks-and-Descriptions
- H7F_AXI_BRESP_HOLD: Keep BRESP stable during backpressure. AMD PG101 v2.0, check 34: AXI_ERRS_BRESP_STABLE. https://docs.amd.com/r/en-US/pg101-axi-protocol-checker/AXI-Protocol-Checks-and-Descriptions
- H7F_AXI_B_AFTER_AW_W: Respond only after both AW and W handshakes. AMD PG101 v2.0, check 32: response dependency. https://docs.amd.com/r/en-US/pg101-axi-protocol-checker/AXI-Protocol-Checks-and-Descriptions

## Limits

- Three selected write-response rules only; a passing result is not complete AXI4-Lite compliance.
- Samples are assumed to describe signals immediately before consecutive ACLK rising edges, beginning in reset. X/Z states, missing edges and sub-cycle behavior are unsupported.
- A finite passive trace cannot prove that VALID generation is independent of READY, rule out deadlock, or establish an unobserved response deadline.
- The checker does not verify read channels, AW/W payload stability, register semantics, reset timing, CDC, or hardware behavior.
- No RTL, commercial simulator, board or customer result is implied. An unfinished response at trace end remains unresolved rather than a protocol violation.