PROPOSED KIT Unbuilt · Hardware validation pending · No purchase available
Build on the PCIe Attach path, with a small host workflow and evidence you can rerun.
For an FPGA team evaluating a host-attached Agilex 5 design and needing a concrete recording and acceptance workflow.
The official PCIe Attach stack supplies important infrastructure. We want to investigate the work between that reference and a repeatable capture file with understandable checks and build provenance.
Request a pilot for this boardResearch price for a defined release and support scope. Hardware, custom integration and any applicable taxes are excluded. Final scope and terms are undecided. No payment or commitment now.
PROPOSED PATH / NOT A TEST RESULT
Framing and checks would have an explicit boundary. Source correctness and transport correctness are separate questions.
- Agilex 5 E-Series 065B Modular / SM72MDK
- Documented Gen4 x4 host path
- One OFS / Quartus / Linux profile to agree
THE PACKAGE WE WANT TO TEST
A small workflow.
Enough evidence to repeat it.
These are proposed deliverables to refine with pilot users, not features already implemented.
Reference build
Our integration source and a reproducible build manifest for the agreed board/tool profile.
Linux recorder
A focused host workflow that preserves the framed data and records its configuration.
Python reader
A small example for inspecting the capture format and the checks associated with it.
Explicit data checks
Sequence and corruption checks plus overflow reporting at a documented boundary.
Repeatable acceptance
Known-pattern tests, process interruption and start/stop cases with honest pass/fail/unknown results.
A defined support scope
Exact versions, dependencies, measured limits and exclusions—established during the pilot.
EXACT SCOPE BEFORE A CLAIM
Define the boundary.
Then test the whole path.
The first experiment
Choose an exact board revision and official PCIe Attach release. Start with a known stream and a small host recorder, then evaluate data checks, process interruption and repeatable restart.
One official PCIe Attach release; FPGA-to-host endpoint scope, not the separate HPS root-port example.
What the checks would establish
PCIe generation is a hardware capability, not a promised file-recording rate. Actual rates, buffering limits and required IP/tool entitlements must be established for the pilot configuration.
There is no benchmark, supported board matrix, real capture sample or guaranteed repair result from Header7F for this concept yet.
HARDWARE CONTEXT
Build on what exists.
The official OFS PCIe Attach flow already exists. We would build a checked application workflow around permitted dependencies, not claim the vendor transport as our invention. Exact software and IP requirements need review.
Board context: Gen4 x4 · Modular PCIe or bench development kit. These are manufacturer-described capabilities, not our measured results.
Manufacturer / board documentationBoard facts reviewed 18 October 2026. Header7F is an independent project; this page does not imply manufacturer endorsement.
HOW A PILOT WOULD START
Describe the real need.
Board access, data source, host setup and the capture problem you actually have.
Choose one configuration.
We discuss fit and define evidence and acceptance criteria before offering paid work.
Review a working result.
A source-based demonstration and clear limits should precede any released-kit claim.
A few practical questions.
Can I download or buy the kit today?
No. This page tests interest in a proposed product. There is no supported release, delivery date or checkout. An enquiry is not an order.
What does the $799 target include?
It is a software-only team-price hypothesis for the stated bounded workflow. Team definition, source/deployment rights, included help, update period and final terms still need agreement. Hardware and custom ports are separate.
Will this fix unknown header type 7f?
It is not a general hardware repair tool. A usable PCIe endpoint is a prerequisite to recording. Use our free diagnostic guide to investigate an inaccessible device.
Do I need to share private data or RTL?
No. A short description of the task and non-confidential configuration is enough for the initial request. The form accepts no uploads.