Pilot in development
Help build the test you wish you had.
We are developing a local regression kit for custom AXI4-Lite peripherals. The first pilot pairs a narrow set of checks with a real integration problem, so the result is useful on a design beyond the demo.
Join the AXI-Lite pilotPlanned checks
Put pressure on the handshake.
Separate address and data
Exercise AW and W on different cycles. Track what was accepted, pair it correctly, and check the resulting response and register effect.
Hold the response
Apply BREADY and RREADY backpressure. Check that a pending response keeps its VALID and payload until the transfer completes.
Interrupt with reset
Reset at defined points in a transaction. Check the interface reset behavior and start fresh accounting for the next sequence.
Declare the register contract
Test writable fields, read-only behavior, strobe handling and error responses against your stated expectations.
The planned package
A route from failure to replay.
- Map the interface. Connect your signals and describe the register behavior in a small manifest.
- Run a focused regression. Start with directed cases, then run a recorded set of random seeds.
- Inspect the finding. Follow the failed check to its transaction, sampled cycle, waveform and expected behavior.
- Replay after the fix. Keep the source, configuration and tool versions attached to the result.
The planned deliverables include source, an adapter example, correct and deliberately faulty peripherals, scenario tests, a JSON/HTML report, a replay path and setup documentation.
A small first release
Start with a scope we can demonstrate.
| Area | Initial target |
|---|---|
| DUT | One unencrypted Verilog/SystemVerilog AXI4-Lite peripheral |
| Interface | 32-bit data, 32-bit address, one clock |
| Traffic | Single-beat, aligned accesses; one pending read and one pending write |
| Registers | Declared read/write and read-only behavior, reset values and error policy |
| Environment | One pinned Linux, Verilator and cocotb setup; exact versions selected during development |
| Execution | Local runs; no hosted simulation or RTL upload required |
Full AXI4, bursts, mixed-language simulation, multiple clocks and hardware timing validation are outside the first pilot. A passing regression will describe the cases run, not certify an entire design.
Before you join
Can I download or buy it today?
The kit is in development. We are collecting relevant problems and selecting design partners. There is no purchase or payment required to send an enquiry.
What will it cost?
Pricing is being tested with prospective users. A paid pilot, if offered, will state its deliverables, support, license and price before you commit.
Do you need my proprietary RTL?
Start with a description of the failure, your simulator and the interface shape. Please keep confidential code, credentials and customer information out of the form. We can discuss a permitted reproduction later.
How will you show that the checks work?
Correct fixtures should pass. Deliberately faulty variants should fail for the expected reason. Independent designs and replayable reports come before a release claim. Read the evidence standard.
Bring us the failure that keeps coming back.
Tell us what stalls, what you have tried, and where a better test would help.
Check fit for the pilot