Why is your PCIe link x8, x1 or “downgraded”? Ask both ends.

The link width is a negotiation, not a spec sheet

Every PCIe link has exactly two ends. One is a downstream port: a root port in the CPU or chipset, or a port on a switch. The other is your device: a GPU, an NVMe drive, an FPGA board. The number on the box describes only one of them.

At power-up, both ends run the same script, the Link Training and Status State Machine (LTSSM). They detect which lanes have a receiver on the other side, agree on a lane count and numbering, and bring the link up at 2.5 GT/s. Only then do they try a faster rate that both advertise. The width you end up with is the smallest of three things:

LTSSM states, in plain words

You rarely see LTSSM states from Linux on a PC; FPGA PCIe IP and protocol analyzers expose them. AMD’s UltraScale PCIe guide, for example, publishes the state encodings on its status interface. Knowing them still explains the symptoms. The width is decided early, and the speed changes later, which is why the two can fail independently.

If you are bringing up an FPGA endpoint that trains at x1, the XDMA stuck at x1 guide shows how to pair this host-side view with the IP’s own LTSSM and negotiated-width debug signals.

Why is my GPU running at x8 instead of x16?

Work through these in order. The first three are configuration, not faults, and they account for the boring answer that is usually correct.

1. The slot is not x16 electrically. Many boards have x16-length slots wired for x8 or x4. The board manual’s slot table is the authority, not the plastic.
2. Lanes are shared. CPU lanes are often split between two slots or between a slot and an M.2 socket. Populate the second slot and the first drops to x8. The manual usually says this in a footnote.
3. Bifurcation is set. A firmware option has split the x16 port into x8x8 or x4x4x4x4 for an adapter card. A GPU in a split slot trains at the width of its piece.
4. The card sits behind a riser, cable or switch. Each adds an end or a connector. Read the link that the GPU actually terminates on. Mining rigs are the extreme case; the riser guide covers why an x1 link can be fine while its cable is not.
5. Signal quality forced a narrower or slower link. This is the case worth real worry. It usually leaves correctable AER errors behind and may change between boots or under load.

The lane-sharing arithmetic is often printed on the spec sheet. Intel lists the CPU lanes of a Core i9-13900K as one x16 or two x8 (plus an x4), and boards built on such chips advertise two x16-length slots that run “x16 or x8/x8”. Install a second card and the first one halves. That is the design, not a defect.

Then there is idle power saving. NVIDIA’s nvidia-smi documentation says a GPU’s current link generation and width may be reduced when the GPU is not in use, and amdgpu exposes PCIe power levels that pair a speed with a width. A reading of 2.5 GT/s on an idle desktop is not, by itself, evidence of a problem. Re-read the link while the GPU is busy.

What the PCIe link speed numbers mean

lspci prints the speed per lane in gigatransfers per second. The generation is the same number in different words, and the encoding explains why 8 GT/s is roughly twice as useful as 5 GT/s rather than 60% better.

Bandwidth is speed × width × encoding efficiency. Losing half the lanes costs the same as dropping one generation. That is why an x8 PCIe 4.0 link and an x16 PCIe 3.0 link land in the same place, and why you should compare both numbers, not just the one in the headline.

PCIe bifurcation: one slot, several links

Bifurcation splits one physical x16 port into several independent links: x8x8, x8x4x4 or x4x4x4x4. It is how a passive four-drive M.2 card works. The card has no switch, so each drive needs its own x4 link from the CPU, and the firmware must be told to create them.

Get it wrong in one direction and only the first drive appears, because the port still trains as one link to the first device it finds. Get it wrong in the other and a GPU that could use x16 trains at x8 or x4. Linux cannot change bifurcation; it is a firmware and board decision made before the OS runs.

In lspci -t, a correctly bifurcated x4x4x4x4 slot usually shows several root ports, each with one device below it at x4. A card with a PCIe switch on it looks different: one upstream link, then a switch with downstream ports. Not every CPU, board or slot supports every split. Check the board manual before buying the adapter.

Triage: find out who limited the link

1. Find the device and its link partner.

   lspci -D -PP -nn | grep -iE "vga|3d|nvme|10ee"

   The -PP path ends with your device; the address before it is the port on the other end of the link, for example 0000:00:01.1/01:00.0. With a switch or riser bridge in between, the immediate partner is the last bridge in the path.

2. Compare LnkCap and LnkSta on both ends.

   sudo lspci -s 0000:01:00.0 -vv | grep -E "LnkCap:|LnkSta:"
   sudo lspci -s 0000:00:01.1 -vv | grep -E "LnkCap:|LnkSta:"

   If the port’s own LnkCap says x8, your x8 link is the port’s maximum, and the investigation is over. If both ends say x16 in LnkCap but LnkSta says x8, look at wiring, lane sharing, bifurcation and signal quality. The lspci -vvv field guide explains the rest of each line.

3. Read the same values from sysfs.

   cd /sys/bus/pci/devices/0000:01:00.0
   grep -H . current_link_speed current_link_width max_link_speed max_link_width

   Speeds read like 16.0 GT/s PCIe and widths are bare numbers. Use these files for scripts and before/after snapshots; they are the kernel’s view of the same registers. A missing file is missing evidence, not zero.

4. Let the kernel name the bottleneck.

   sudo dmesg | grep -i "available PCIe bandwidth"

   At enumeration, Linux prints this line for an endpoint whose bandwidth is limited somewhere on its path, and some drivers print it at load time. It names the slowest link and the device where that link sits. That address is often a bridge or root port, not your card. No line at all usually means the kernel found nothing limiting.

5. Re-read under load.

   Start a workload you already trust, then repeat step 2 for the device. If the speed and width rise to what the slot supports, the idle reading was power saving. If either falls under load, keep going.

6. Check AER counters on both ends.

   for dev in 0000:01:00.0 0000:00:01.1; do
     grep -H . /sys/bus/pci/devices/$dev/aer_dev_correctable
   done

   Rising correctable errors such as receiver errors, bad TLPs, bad DLLPs or replay timeouts point to signal quality. Take a reading before and after the same workload; a total alone has no timeline.

7. Check firmware and the manual, then change one thing.

   Look for a forced PCIe generation, a bifurcation setting and the slot-sharing table. Then test one physical change at a time with the system powered off: another slot, no riser, a reseated card. Save the lspci output from each run.

Paste the lspci -xxx bytes from either end into the PCI config space decoder to see Link Capabilities, Link Status and Link Control 2 decoded side by side, entirely in your browser.

Annotated example: an x16 GPU that is fine at x8

$ lspci -D -PP -nn | grep -i vga
0000:00:01.1/01:00.0 VGA compatible controller [0300]: ...  [10de:xxxx]
#            ^ the port on the other end of this link is 0000:00:01.1

$ sudo lspci -s 01:00.0 -vv | grep -E "LnkCap:|LnkSta:"
LnkCap: Port #0, Speed 16GT/s, Width x16, ASPM L1, Exit Latency L1 <4us
LnkSta: Speed 2.5GT/s (downgraded), Width x8 (downgraded)
#       ^ idle power saving: re-read under load before judging the speed
#                                   ^ below this card's own x16 maximum

$ sudo lspci -s 00:01.1 -vv | grep -E "LnkCap:|LnkSta:"
LnkCap: Port #1, Speed 16GT/s, Width x8, ASPM L1, Exit Latency L1 <8us
LnkSta: Speed 2.5GT/s, Width x8
#       ^ the port itself is x8: this slot is split or wired x8.
#         No "(downgraded)" here: lspci omits it on downstream ports.

Read it bottom-up. The root port can only do x8, so the GPU’s “downgraded” width is the platform’s choice, not a fault. The speed reading needs a second capture under load. If the board manual says this slot should be x16 with nothing else installed, check the bifurcation and slot-sharing settings next.

Questions

Does “LnkSta downgraded” in lspci mean my card is broken?

No. It means the current link is slower or narrower than that one device’s own maximum. Check the upstream port’s LnkCap: if the port or slot is x8, an x8 result is expected. It becomes a fault only when both ends and the wiring support more and the link still comes up lower.

Why does my GPU show 2.5 GT/s at idle?

Many GPUs lower their PCIe link to save power when idle and raise it under load. NVIDIA documents that the current link generation and width may both be reduced when the GPU is not in use. Re-read LnkSta, or current_link_speed and current_link_width in sysfs, while the GPU is busy before treating the idle value as a problem.

Does a GPU at x8 instead of x16 lose performance?

The link has half the lanes, so the peak transfer rate halves. Whether your application notices depends on how much data it moves across PCIe compared with the work done on the card. Measure your own workload at both widths rather than relying on a generic figure.

What is PCIe bifurcation and do I need it?

Bifurcation is a firmware setting that splits one x16 port into several smaller links, such as x8x8 or x4x4x4x4. You need it for passive multi-drive M.2 adapters and some dual-device risers. You do not need it for a single GPU, and leaving it enabled can make that GPU train narrower.

How do I check PCIe link speed and width in Linux?

Run sudo lspci -s <address> -vv and read the LnkCap and LnkSta lines, or read current_link_speed, current_link_width, max_link_speed and max_link_width under /sys/bus/pci/devices/<address>/. Do the same for the upstream port.

Can I force a PCIe link to retrain on Linux?

The port above the device has a Retrain Link bit in its Link Control register. The kernel sets it in some quirks, and since Linux 6.13 its bandwidth controller can change a port’s target speed and retrain. Retraining changes live state, can drop the device and cannot add lanes that are not wired. Save evidence first; a cold boot with the corrected slot or firmware setting is the real test.