Address and data do not arrive as a pair.

Updated 18 October 2026

Count accepted transfers.

On the rising clock edge, AWVALID with AWREADY accepts the address; WVALID with WREADY accepts the data. Those handshakes can happen on different edges. Keep separate records of accepted address and data, then pair them in order.

A write response must follow the required accepted inputs. Checking only whether AWVALID and WVALID happen to be high together can miss accepted transfers, reuse a stale address or count a transaction twice.

Exercise both arrival orders.

1. Assert AWVALID first. Hold it and its address until accepted. Introduce WVALID several cycles later.
2. Repeat with WVALID first, keeping its data and strobes stable until accepted.
3. Present both together, then vary response backpressure and repeat.

Check the register effect as well.

Use distinct addresses and recognizable data patterns. Confirm that each accepted address/data pair creates exactly one response and the declared register update. A clean handshake with data written to the wrong register is still a useful failure.

Keep a response watchdog if your project needs one, but label its deadline as a project expectation. Do not turn an arbitrary cycle budget into a protocol requirement.

Reference: AMD AXI protocol-check descriptions, including channel stability and write-response dependencies.

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