A stalled response is still a promise.

Updated 18 October 2026

The edge decides.

For an AXI channel, a transfer occurs when VALID and READY are both high at the sampling edge. VALID alone offers a transfer. READY alone does not accept one. When VALID is high and READY is low, the source must keep the offer and its payload stable until acceptance.

Apply the stall after the response appears.

For the read channel, hold RREADY low while RVALID is asserted. Watch RVALID, RDATA and RRESP across each stalled cycle. For the write-response channel, do the same with BREADY, BVALID and BRESP.

Count handshakes, not VALID cycles.

A response held for three cycles is not three responses. Increment your accepted-transfer count at the handshake. Separately monitor stability while it waits. This distinction catches both disappearing responses and scoreboards that overcount correct behavior.

Try short stalls and longer ones, then release READY. Keep reset as a separate scenario with explicit reset rules; do not apply an ordinary stalled-transfer assertion blindly across reset.

Reference: AMD AXI protocol-check descriptions for response stability and VALID persistence.

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