Open Console
HEADER7F / VISUAL GUIDES · AXI & PCIe

VISUAL GUIDES · AXI & PCIe

See the handshake. Spot the fault.

Compare a response that waits with one that disappears, changes or arrives too early. Each diagram shows what to notice and the cycle to inspect.

Start with a response that waits correctly, then compare the faults. These synthetic examples are replayed by our trace monitor. Open any diagram’s details for the explanation, source and downloads.

01 / BOTH ARRIVAL ORDERS

Two channels. One write response.

The address and data can be accepted on different edges. The response follows both; it stays available while the receiver is not ready.

Keep the response until it is acceptedSelected checks passed

Synthetic example · not a hardware measurement

Synthetic AXI4-Lite samples: address accepted at cycle 2, data at 4, BVALID stays high through stalled cycles 5 and 6, and BREADY accepts the response at 7.

Scroll sideways to see the full diagram

What to notice

The receiver waits. BVALID and BRESP stay steady until the response is accepted at cycle 7.

Details & downloads: Keep the response until it is accepted
  • Address is accepted at cycle 2 and write data at cycle 4. BVALID first appears at cycle 5, after both handshakes.
  • BREADY is low at cycles 5 and 6. BVALID remains 1 and BRESP remains 00 (OKAY), including acceptance at cycle 7.
  • The monitor finds no violation in its three selected write-response checks. This does not establish complete AXI4-Lite compliance.

Each numbered column is one supplied sample immediately before a consecutive ACLK rising edge. The clock is not drawn. Connecting lines are schematic; edge placement and behavior between samples were not measured. All eight input signals are retained, including BRESP when BVALID is low. These are hand-authored synthetic samples, not captured RTL or hardware.

Download SVG: Keep the response until it is acceptedWaveJSON source: Keep the response until it is accepted

References: Replayable input JSON · Executed selected-check report · Checker source (MIT) · AMD PG101: selected protocol checks · Arm AXI and ACE specification, IHI 0022H

Rendered with WaveDrom 3.7.0 · Open-source notices

Write data can arrive before the addressSelected checks passed

Synthetic example · not a hardware measurement

Synthetic AXI4-Lite samples: write data is accepted at cycle 2, address at 4, and the response stays stable until acceptance at 7.

Scroll sideways to see the full diagram

What to notice

Data first is allowed. The response follows both inputs and is accepted at cycle 7.

Details & downloads: Write data can arrive before the address
  • The W handshake is at cycle 2; the AW handshake is at cycle 4. The address and data channels are independent.
  • BVALID waits until cycle 5, after both earlier handshakes, then remains asserted through backpressure and acceptance at cycle 7.
  • No violation is observed in the three selected checks. The trace does not prove how the design generates VALID independently of READY.

Each numbered column is one supplied sample immediately before a consecutive ACLK rising edge. The clock is not drawn. Connecting lines are schematic; edge placement and behavior between samples were not measured. All eight input signals are retained, including BRESP when BVALID is low. These are hand-authored synthetic samples, not captured RTL or hardware.

Download SVG: Write data can arrive before the addressWaveJSON source: Write data can arrive before the address

References: Replayable input JSON · Executed selected-check report · Checker source (MIT) · AMD PG101: selected protocol checks · Arm AXI and ACE specification, IHI 0022H

Rendered with WaveDrom 3.7.0 · Open-source notices

02 / REPLAYABLE FAULTS

Which promise was broken?

These three deliberately altered traces trigger different checks. A later successful handshake does not erase an earlier violation.

Fault: the response disappears before acceptanceFault at cycle 6

Synthetic example · not a hardware measurement

Injected AXI4-Lite fault: BVALID is 1 with BREADY 0 at cycle 5, but BVALID falls to 0 at cycle 6 before the response is accepted.

Scroll sideways to see the full diagram

What to notice

At cycle 6, BVALID drops while the receiver is still waiting. The response must stay available.

Details & downloads: Fault: the response disappears before acceptance
  • Cycle 5 has BVALID=1 and BREADY=0: the response is waiting for acceptance.
  • At cycle 6, BVALID falls to 0 while BREADY is still 0. The monitor reports H7F_AXI_BVALID_HOLD at cycle 6.
  • BVALID returning for acceptance at cycle 7 does not erase the earlier violation.

Each numbered column is one supplied sample immediately before a consecutive ACLK rising edge. The clock is not drawn. Connecting lines are schematic; edge placement and behavior between samples were not measured. All eight input signals are retained, including BRESP when BVALID is low. These are hand-authored synthetic samples, not captured RTL or hardware.

Download SVG: Fault: the response disappears before acceptanceWaveJSON source: Fault: the response disappears before acceptance

References: Replayable input JSON · Executed selected-check report · Checker source (MIT) · AMD PG101: selected protocol checks · Arm AXI and ACE specification, IHI 0022H

Rendered with WaveDrom 3.7.0 · Open-source notices

Fault: the response changes while waitingFault at cycle 6

Synthetic example · not a hardware measurement

Injected AXI4-Lite fault: BVALID remains high but BRESP changes from binary 00 at cycle 5 to 10 at cycle 6 while BREADY is 0.

Scroll sideways to see the full diagram

What to notice

At cycle 6, BRESP changes from OKAY to SLVERR before the receiver accepts the response.

Details & downloads: Fault: the response changes while waiting
  • BVALID is asserted while BREADY remains low at cycles 5 and 6.
  • BRESP changes from 00 (OKAY) at cycle 5 to 10 (SLVERR) at cycle 6. The monitor reports H7F_AXI_BRESP_HOLD at cycle 6.
  • The displayed bus values are the actual sampled BRESP values, including samples where BVALID is low.

Each numbered column is one supplied sample immediately before a consecutive ACLK rising edge. The clock is not drawn. Connecting lines are schematic; edge placement and behavior between samples were not measured. All eight input signals are retained, including BRESP when BVALID is low. These are hand-authored synthetic samples, not captured RTL or hardware.

Download SVG: Fault: the response changes while waitingWaveJSON source: Fault: the response changes while waiting

References: Replayable input JSON · Executed selected-check report · Checker source (MIT) · AMD PG101: selected protocol checks · Arm AXI and ACE specification, IHI 0022H

Rendered with WaveDrom 3.7.0 · Open-source notices

Fault: a response arrives before write dataFault at cycle 3

Synthetic example · not a hardware measurement

Injected AXI4-Lite fault: the address handshake occurs at cycle 2, BVALID and BREADY accept a response at 3, but write data is not accepted until 4.

Scroll sideways to see the full diagram

What to notice

The response is accepted at cycle 3. The write data is not accepted until cycle 4.

Details & downloads: Fault: a response arrives before write data
  • AW is accepted at cycle 2. BVALID is already asserted and accepted at cycle 3, before the W handshake at cycle 4.
  • The monitor reports H7F_AXI_B_AFTER_AW_W at cycle 3. Both address and data must have earlier unmatched handshakes before BVALID.
  • A later write-data handshake cannot make the earlier response valid.

Each numbered column is one supplied sample immediately before a consecutive ACLK rising edge. The clock is not drawn. Connecting lines are schematic; edge placement and behavior between samples were not measured. All eight input signals are retained, including BRESP when BVALID is low. These are hand-authored synthetic samples, not captured RTL or hardware.

Download SVG: Fault: a response arrives before write dataWaveJSON source: Fault: a response arrives before write data

References: Replayable input JSON · Executed selected-check report · Checker source (MIT) · AMD PG101: selected protocol checks · Arm AXI and ACE specification, IHI 0022H

Rendered with WaveDrom 3.7.0 · Open-source notices

03 / BEFORE ENUMERATION

Collect the events before drawing conclusions.

For a missing PCIe card, start with measured power, clock, reset, configuration and host events. These bands are a checklist, with no assumed timing or required order.

Build one startup record across three evidence bandsEvidence checklist

Illustrative bands · no timing scale or assumed order

Three qualitative PCIe startup evidence bands: board power, reference clock and PERST#; FPGA configuration and core reset; and link state with host discovery. No voltage levels or numeric timing are claimed.

Scroll sideways to see the full diagram

What to notice

Collect board, endpoint and host events on one measured timeline. These bands show what to collect.

Details & downloads: Build one startup record across three evidence bands
  • Board evidence: measure power validity, reference-clock stability and PERST# assertion/deassertion at the actual interface, with its documented polarity.
  • Endpoint evidence: record FPGA configuration completion and the applicable core or user reset release. Programming success alone does not establish readiness for host configuration requests.
  • Link and host evidence: record link-up or documented LTSSM evidence alongside the first relevant host messages and the enumerated inventory.
  • Correlate the actual events in a measured timeline. These bands are a collection checklist; they deliberately do not draw an assumed legal power/reset waveform or prescribe an event order.

Illustrative evidence bands, not measured signals or a required sequence. Their equal spans do not establish durations, simultaneity, polarity or ordering. On the real board, place measured power, clock, reset, configuration, link and host events on a shared timeline; identify inferred or unavailable observations. Use the timing requirements for the exact FPGA, IP release, board and host. There is no universal “100 ms” patch.

Download SVG: Build one startup record across three evidence bandsWaveJSON source: Build one startup record across three evidence bands

References: FPGA missing from lspci: readiness investigation · AMD PG054: readiness during enumeration · AMD PG054: configuration and reset timing requirements · AMD PG054: scope of closed-system workarounds

Rendered with WaveDrom 3.7.0 · Open-source notices

Put the pattern to work.

Use the backpressure guide to check what happens when your receiver waits. Each diagram’s details include a downloadable image, source and supporting evidence.

Message us